1. Field of the Invention
This invention is related to semiconductor integrated circuit devices and a manufacturing technique therefor and, in particular, to a method of attaining high integration, high reliability and high performance of a nonvolatile semiconductor memory device.
2. Description of Related Art
Since flash memory devices functioning similarly to EEPROMs (Electrically Erasable Programmable Read Only Memory) are capable of electrical writing and erasing and are very portable and impact resistant, the demand therefor has recently increased rapidly for use in mobile phones, portable personal computers, digital cameras and in microcomputers in the engine control systems of automobiles.
To improve the marketability of such devices, reduction of the memory cell area is essential for reducing the cost thereof and various memory cell systems have been proposed for attaining the same. One such system is a virtual ground type memory cell using a 3-layered polysilicon gate as disclosed, for example, in JP-A No. 200242/1999.
The memory cell of the type described above comprises, as shown in FIG. 60, a well 601 in a silicon substrate 600, source and drain diffusion layer regions 605, 605xe2x80x2 in the well, and three gates including a floating gate 603b as a first gate comprising a polysilicon film formed on the well, a control gate 611a as a second gate, and a third gate 607a for controlling an erasing gate and a split channel.
Each of the gates 603b, 611a, and 607a comprises a polysilicon film, and are isolated from the well 601 by insulator films 602, 606a, 606b, 608a, and 610. The control gates 611a are connected in a row to constitute word lines. The source and drain diffusion layer 605 is a virtual ground type having the diffusion layer of an adjacent memory cell in common to reduce the pitch in the direction of the row. The third gates 607a are disposed in parallel with the channels and perpendicular to the word lines 611a. 
Upon writing, positive voltage independent of each other is applied to the word line 611a, the drain 605 and the third gate 607a while setting the well 601 and the source 605xe2x80x2 to 0 V. Thus, hot electrons are generated in a channel at the boundary between the third gate and the floating gate and they are injected into the floating gate 603b. This increases the threshold voltage of the memory cell. Upon erasing, a positive voltage is applied to the third gate 607a while setting the word line 611a, the source 605xe2x80x2, the drain 605 and the well 601 to 0 V. This discharges electrons from the floating gate 603b to the third gate 607a to lower the threshold voltage. xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d of information is determined by changing the threshold voltage of the memory cell transistor.
Problems arise, however, when to the density is increased in the nonvolatile semiconductor memory device described above.
At first, this concerns the reduction in the size of the memory cell. When it is intended to further reduce the size of the split gate type memory cell, it is important to reduce the gate length for the floating gate 603b and the third gate 607a. For this purpose, it is necessary to reduce the thickness of the gate insulator films 602 and 606a and improve the punch through resistance. However, no discussion has been made on the thickness of each gate insulator film.
Next, there is a problem in improving the reliability. In a flash memory, it has to be ensured that the data is held for more than 10 years after conducting writing/erasing cycles for 100,000 cycles or more. Elimination of data is caused by leakage of electrons accumulated in the floating gate.
While there are present plural modes for the cause of the leakage, the present inventors have found that the mode where electrons accumulate in the floating gate and incidentally leak at certain bits is most problematic. Such leakage has a correlation with the thickness of the gate insulator film 602 between the floating gate and the substrate, the so-called tunnel film, and the number of failure bits increases as the thickness of film is reduced.
According to the study made by the present inventors, it is necessary to increase the film thickness of the tunnel insulator film 602 to 9 nm or more in order to hold the data for 10 years, particularly in multi-level storage of 2 bits in one memory cell. Accordingly, to minimize the size of these memory devices, the thickness of the gate insulator films 602 and 606a must be considered.
The third problem is the increase in the number of manufacturing steps. A usual flash memory has a peripheral circuit for applying voltage to the memory cell or conducting logic operations. In the circuit for applying the voltage to the cell, since a high voltage, for example, of 18 V is applied to the word line, a MOS (Metal Oxide Semiconductor) transistor constituting the circuit has a high voltage withstanding structure using a thick gate insulator film of, for example, 25 nm. On the other hand, in the circuit for conducting the logic operation, the applied voltage is, for example, 3 V of an external power source voltage and high-speed operation is required. Therefore, the thickness of the gate insulator film of the MOS constituting the circuit for conducting the logic operation is extremely thin compared with the structure for withstanding high voltage. Thus, improved manufacturing methods are needed to form the two kinds of gate insulator films for the peripheral circuit and the two kinds of gate insulator films for the memory cell to simplify production and reduce the cost thereof.
As described above, the development of a new nonvolatile semiconductor memory device and a manufacturing method therefor are desirable with respect to gate insulator films of a split gate type memory cell.
A nonvolatile semiconductor memory device of reduced size and improved reliability are desirable.
Simplified production steps for producing such nonvolatile semiconductor memory devices are also desirable.
In a first preferred embodiment, the nonvolatile semiconductor memory device has a plurality of memory cells each comprising a first conduction type well formed in a silicon substrate, source/drain diffusion layer regions of a second conduction type formed in the well, a channel formed in a direction perpendicular to the diffusion layer region, a floating gate as a first gate formed on the silicon substrate comprising an insulator film, a control gate as a second gate comprising an insulator film disposed on the floating gate, a word line formed by connection of the control gate, and a third gate having a function different from those of the floating gate and the control gate and comprising an insulator film insulative with respect to the silicon substrate, the floating gate and the control gate, wherein the thickness of a gate insulator film for isolating the floating gate from the well is made larger than the thickness of the gate insulator film isolating the third gate from the well.
Preferably the third gate controls the split channel. Alternatively, the third gate functions as an erasing gate and to control the split channel.
The insulator film between the third gate and the well is formed by the same process step as the gate insulator film disposed on the low voltage area of the peripheral circuit region.
Alternatively, the insulator film between the floating gate and the well is preferably formed by the same process step as the gate insulator film disposed on the low voltage area of the peripheral circuit region.
The thickness of the insulator film between the floating gate and the third gate is preferably larger than the insulator film thickness between the floating gate and the well. Alternatively, the thickness of the insulator film between the floating gate and the third gate is preferably substantially identical to the insulator film thickness between the floating gate and the well.
In this first exemplary embodiment, the insulator film between the floating gate and the third gate preferably comprises a silicon oxide film containing nitrogen.
In a second preferred embodiment, the nonvolatile semiconductor memory device comprises (1) a plurality of memory cells each comprising a first conduction type well formed in a silicon substrate, source/drain diffusion layer regions of a second conduction type formed in the well, a channel formed in a direction perpendicular to the diffusion layer region, a floating gate as a first gate comprising an insulator film disposed on the silicon substrate, a control gate as a second gate comprising an insulator film disposed on the floating gate, a word line formed by connection of the control gate, and a third gate of having a function different from the floating gate and the control gate and comprising an insulator film isolating the silicon substrate, the floating gate and the control gate, and (2) a peripheral circuit region for operating the memory cell, wherein the peripheral circuit region comprises MOS transistors of a low voltage system and a high voltage system in which the film thickness of the gate insulator film for the low voltage system MOS transistor is substantially identical i.e., formed in the same process step and comprising part of the same layer as the gate insulator film between the third gate and the well, and the thicknesses of the insulator films are larger in the order of (i) the gate insulator film for the high voltage system MOS transistor, (ii) the gate insulator film between the floating gate and the well, and (iii) the gate insulator film between the third gate and the well.
In a third preferred embodiment, the nonvolatile semiconductor memory device comprises (1) a plurality of memory cells each comprising a first conduction type well formed in a silicon substrate, source/drain diffusion layer regions of a second conduction type formed in the well, a channel formed in a direction perpendicular to the diffusion layer region, a floating gate as a first gate comprising an insulator film disposed on the silicon substrate, a control gate as a second gate comprising an insulator film disposed on the floating gate, a word line formed by connection of the control gate, and a third gate having a function different from the floating gate and the control gate and comprising of an insulator film isolating the silicon substrate, the floating gate and the control gate, and (2) a peripheral circuit region for operating the memory cell, wherein the peripheral circuit region comprises MOS transistors of a low voltage system and a high voltage system in which the film thickness of the gate insulator film for the low voltage system MOS transistor is substantially identical i.e., formed in the same process step and comprising part of the same layer as the gate insulator film between the floating gate and the well, and the thicknesses of the insulator films are larger in the order of (i) the gate insulator film for the high voltage system MOS transistor, (ii) the gate insulator film between the floating gate and the well, and (iii) the gate insulator film between the third gate and the well.
In the nonvolatile semiconductor memory device of this third preferred embodiment, the memory cell conducts writing by the charging of hot electrons from the channel to the floating gate and erasing by tunnel emission from the floating gate to the well. Alternatively, the memory cell conducts writing by the charging of hot electrons from the channel to the floating gate and erasing by tunnel emission from the floating gate to the third gate.
Alternatively, a nonvolatile semiconductor memory device of the present invention preferably comprises a memory cell comprising a first conduction type well formed in a silicon substrate, source/drain diffusion layer regions of a second conduction type formed in the well, a channel formed in a direction perpendicular to the diffusion layer region, a floating gate as a first gate formed on the silicon substrate by way of an insulator film, a control gate as a second gate formed by way of an insulator film to the floating gate, a word line formed by connection of the control gate, and a third gate of a function different from the floating gate and the control gate and formed by way of an insulator film to the silicon substrate, the floating gate and the control gate, wherein the thickness of the gate insulator film for isolating the floating gate from the well is larger compared with the thickness of the gate insulator film for isolating the control gate from the well.
In this case, the third gate preferably is an erasing gate.
Further, the thickness of the insulator film between the floating gate and the control gate preferably is larger compared with the film thickness between the floating gate and the well.
Alternatively, the thickness of the insulator film between the floating gate and the control gate is substantially identical with the thickness between the floating gate and the well.
In this preferred example, the insulator film between the floating gate and the third gate is a silicon oxide film containing add nitrogen.
In the operation system of this case, writing to the memory cell is conducted by injection of channel hot electrons from the channel to the floating gate and erasing from the memory cell is conducted by tunnel emission from the floating gate to the third gate.
Alternatively, the nonvolatile semiconductor memory device of the present invention preferably comprises a memory cell comprising a first conduction type well formed in a silicon substrate, source/drain diffusion layer regions of a second conduction type formed in the well, a channel formed in a direction perpendicular to the diffusion layer region, a floating gate as a first gate formed on the silicon substrate by way of an insulator film, and a control gate as a second gate formed by way of an insulator film to the floating gate, and the channel, wherein the thickness of the gate insulator film for isolating the floating gate from the well preferably is larger compared with the thickness of the gate insulator film for isolating the control gate from the well.
In this case, the control gate preferably is a gate for controlling a split channel.
Further, writing to the memory cell is conducted by injection of channel hot electrons from the channel to the floating gate and erasing from the memory cell is conducted by tunnel emission from the floating gate to the drain.
Further, the gate insulator film between the floating gate and the well and the gate insulator film between the third gate and the well may be formed in the same manufacturing step that produces the gate insulator film of a MOS transistor in a peripheral circuit low voltage portion.